The present invention relates to voltage level shifters for electronic devices and, more particularly, to a level shifter circuit that operates even if a supply voltage drops below a level necessary to generate a shifted signal.
With rapid advancements in the field of integrated circuits (ICs), specifications for ICs also have changed. Although an internal operating voltage of 5V was common in conventional ICs, an internal operating voltage for IC devices today is usually 3.3V or 1.8V. In a multi-voltage system, integration of more than one type of IC in a functional system is common. Hence, there is a requirement for a level shifter circuit for shifting the voltage level at the output of one IC to the voltage level at the input of another IC. The output of an IC that operates at a higher voltage level may be provided to another IC that operates at a lower voltage level. In this case, the voltage needs to be ramped down to a lower level. Similarly, when the output of an IC that operates at a lower voltage level is input to an IC that has a higher operating voltage, the voltage needs to be ramped up.
A limitation of a conventional level shifter is if the input levels are at intermediate levels, the shifter cannot provide correct output characteristics. This may cause excessive leakage current. Further, a conventional level shifter may fail to operate during a power ramp-up. For instance, core supply or analog supply may not be switched ON/OFF or be below/above a threshold level required for the level shifter to operate. Further, an external power ON is not guaranteed when supply voltages ramp down. In such cases, the conventional level shifter may attain undefined output states and may cause indefinite current flow in the circuit. Also, the level shifter may exceed reliability limits, resulting in output degradation.
In view of the foregoing, there is a need for a level shifter circuit that supports specific supply sequencing without leading to extra provisions on system boards. It is desirable that the level shifter supports power supply sequence independent designs and overcomes constraints associated with dependence on external power on a reset input. It is also desirable that the level shifter output is at a defined state during power ramp up/down, and that the level shifter has the ability to reduce the leakage current during supply ramp up/down.